Apparatus for removing a halogen-containing residue

ABSTRACT

The invention provides for a method and integrated system for removing a halogen-containing residue from a substrate comprising etching the substrate, heating the substrate and exposing the heated substrate to a plasma that removes the halogen-containing residue.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of co-pending U.S. patent applicationSer. No. 10/777,026, filed Feb. 11, 2004, which claims the benefit ofU.S. Provisional Application No. 60/447,406 filed Feb. 14, 2003. Each ofthe aforementioned related patent applications is herein incorporated byreference.

BACKGROUND OF THE DISCLOSURE

1. Field of the Invention

The present invention generally relates to a method and apparatus forfabricating devices on a semiconductor substrate. More specifically, thepresent invention relates to a method and apparatus for removinghalogen-containing residue after plasma etching a conducting orsemiconducting layer.

2. Description of the Related Art

Ultra-large-scale integrated (ULSI) circuits may include more than onemillion electronic devices (e.g., transistors) that are formed on asemiconductor substrate, such as a silicon (Si) wafer, and cooperate toperform various functions within the device. Typically, the transistorsused in the ULSI circuits are complementary metal-oxide-semiconductor(CMOS) field effect transistors. A CMOS transistor has a gate structurecomprising a polysilicon gate electrode and gate dielectric and isdisposed between a source region and drain regions that are formed inthe wafer.

Fabrication of the electronic devices comprises etch processes in whichone or more layers of a film stack (e.g., film stack of the gatestructure) are plasma etched and removed, either partially or in total.During plasma etch processes, the layers (e.g., layers of silicon,polysilicon, hafnium dioxide (HfO₂), silicon dioxide (SiO₂), and thelike) are typically exposed to etchants comprising at least onehalogen-containing gas, such as hydrogen bromide (HBr), chlorine (Cl₂),carbon tetrafluoride (CF₄), carbon monoxide (CO), and the like. Suchprocesses cause a halogen-containing residue to build up on the surfacesof the etched features, etch masks, and elsewhere on the wafer.

When exposed to a non-vacuumed environment (e.g., within factoryinterfaces that interconnect various wafer processing systems) and/orduring consecutive processing, the halogen-containing residues releasegaseous halogens and halogen-based reactants (e.g., bromine (Br₂),chlorine, hydrogen chloride (HCl), and the like). The released halogensand halogen-based reactants cause corrosion and particle contaminationof the interior of the processing systems and factory interfaces, aswell as corrosion of metallic layers on the substrate. Cleaning of theprocessing systems and factory interfaces and replacement of thecorroded parts is a time consuming and expensive procedure.

Therefore, there is a need in the art for a method of removing ahalogen-containing residue from a substrate during fabrication of CMOStransistors and other devices used in the integrated circuits.

SUMMARY OF THE INVENTION

A method and apparatus for removing a halogen-containing residue from asubstrate comprises pre-heating the substrate in an atmosphere of oxygenand nitrogen and exposing the pre-heated substrate in a remote plasmareactor to a gas (or gas mixture) comprising oxygen, nitrogen, and anoptional hydrogen-containing gas.

BRIEF DESCRIPTION OF THE DRAWINGS

The teachings of the present invention can be readily understood byconsidering the following detailed description in conjunction with theaccompanying drawings, in which:

FIG. 1 depicts a flow diagram of a method of removing ahalogen-containing residue in accordance with the present invention;

FIGS. 2A-2D, together, depict a sequence of schematic, cross-sectionalviews of a substrate having a gate structure of a field effecttransistor being formed in accordance with the method of FIG. 1;

FIG. 3 depicts a schematic diagram of an exemplary remote plasmaprocessing apparatus of the kind used in performing portions of theinventive method; and

FIG. 4 depicts a schematic plan view of an integrated platform used toperform the method of the present invention.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures.

It is to be noted, however, that the appended drawings illustrate onlyexemplary embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

DETAILED DESCRIPTION

The present invention is a method and apparatus for removing ahalogen-containing residue (i.e., a residue containing bromine (Br),chlorine (Cl), and the like) after plasma etching a layer on asemiconductor substrate, e.g., silicon (Si) wafer.

The invention increases the productivity of fabricating integratedelectronic devices and is generally used to protect factory interfaces,processing equipment, and metallic layers of the thin film electronicdevices from corrosion and particle contamination caused byhalogen-based reactants (e.g., Br₂, Cl₂, and the like). Such reactantsare formed when the wafers comprising a halogen-containing residue areexposed, even momentarily, to a non-vacuumed portion (e.g., atmosphericpressure portion) of a facility for fabricating devices on semiconductorwafers, e.g., semiconductor fabrication process.

FIG. 1 depicts a flow diagram of a method 100 of removing ahalogen-containing residue in accordance with the present invention. Inone illustrative embodiment, the method 100 comprises processesperformed upon a film stack of a gate structure of a field effecttransistor, such as a complementary metal-oxide-semiconductor (CMOS)transistor and the like. Although the invention is described for useduring gate structure fabrication, the invention also finds use wherevera halogen-containing residue is to be removed, e.g., shallow trenchisolation formation. For best understanding of this embodiment of theinvention, the reader should refer simultaneously to FIGS. 1 and 2A-2D.

FIGS. 2A-2D, together depict a sequence of schematic, cross-sectionalviews of a substrate having a gate structure being formed in accordancewith the method 100 of FIG. 1. The cross-sectional views in FIGS. 2A-2Drelate to individual processing steps that are used to form the gatestructure. Conventional sub-processes (e.g., exposure and development ofphotoresist, wafer cleaning procedures, and the like) are well known inthe art and, as such, are not shown in FIG. 1 and FIGS. 2A-2D. Theimages in FIGS. 2A-2D are not depicted to scale and are simplified forillustrative purposes.

The method 100 starts at step 101 and proceeds to step 102 when a filmstack 202 is formed on a wafer 200 (FIG. 2A). The wafer 200, e.g., asilicon wafer, comprises doped source and drain regions 232 and 234 thatare separated by a channel region 236 of the CMOS transistor. Theseregions are depicted for orientation purposes and are generally notformed until after the gate structure is formed. In an alternativeembodiment, the wafer 200 may further comprise a spacer film (notshown). The spacer film generally is used to protect the channel region236 from diffusive contaminants (e.g., oxygen (O₂) and the like) thatmay be contained in a gate dielectric layer 204. The spacer film may beformed from silicon dioxide (SiO₂), silicon nitride (Si₃N₄), and thelike.

The film stack 202 comprises a doped polysilicon (Si) layer 206 and adielectric layer 204, e.g., hafnium dioxide (HfO₂), silicon dioxide(SiO₂), and the like. Other dielectric materials may also be used. Inone illustrative embodiment, the polysilicon layer 206 and dielectric204 are formed to a thickness of about 500 to 6000 Angstroms and about20 to 60 Angstroms, respectively. Such layers 204 and 206 may beprovided using a deposition technique, such as atomic layer deposition(ALD), chemical vapor deposition (CVD), and the like.

At step 104, a patterned mask 214 is formed on the polysilicon layer 206(FIG. 2B). The mask 214 is formed in the region 220 to define thelocation and topographic dimensions of a gate electrode of the gatestructure being formed using method 100. Further, the mask 214 protectsthe channel region 236 and portions of the source and drain regions 232and 234 that are disposed in the region 220, while exposing the adjacentregions 222 of the wafer 200. The mask 214 is generally a hard maskformed from a material that is stable at the wafer temperatures up to500° C. The suitable hard mask materials comprise dielectric materials,silicon dioxide, Advanced Patterning Film™ (APF) available from AppliedMaterials, Inc. of Santa Clara, and the like. In one illustrativeembodiment, the mask 214 is formed from silicon dioxide or siliconnitride. Alternatively, in some applications, the mask 214 may be formedfrom photoresist. Examples of processes for applying various hard andphotoresist masks are described, in commonly assigned U.S. patentapplication Ser. No. 10/245,130, filed Sep. 16, 2002 and U.S. patentapplication Ser. No. 09/590,322, filed Jun. 8, 2000, which areincorporated herein by reference.

At step 106, the polysilicon layer 206 is etched and removed in theregions 222 (FIG. 2C). A remaining portion of the layer 206 forms in theregion 220 a gate electrode 216. Step 106 uses the mask 214 as an etchmask and may use the dielectric layer 204 as an etch stop layer. In oneillustrative embodiment, step 106 performs a plasma etch process using agas (or gas mixture) comprising at least one of hydrogen bromide (HBr),chlorine (Cl₂), carbon tetrafluoride (CF₄), and the like. Herein theterms “gas” and “gas mixture” are used interchangeably. Step 106 can beperformed, for example, using a Decoupled Plasma Source (DPS) reactor ofthe CENTURA® integrated semiconductor wafer processing system availablefrom Applied Materials, Inc. of Santa Clara, Calif. The DPS reactor usesan inductive source to produce high-density plasma and comprises asource of radio-frequency (RF) power to bias the wafer.

In one embodiment, using the DPS reactor, step 106 provides hydrogenbromide at a rate of 20 to 300 sccm and chlorine at a rate of 20 to 300sccm (i.e., a HBr:Cl₂ flow ratio ranging from 1:15 to all HBr), as wellas nitrogen (N₂) at a rate of 0 to 200 sccm. Further, step 106 applies200 to 3000 W of plasma power and 0 to 300 W of bias power and maintainsa wafer temperature at 0 to 200° C. and a pressure in the reactionchamber at 2 to 100 mTorr. One exemplary process provides HBr at a rateof 40 sccm and Cl₂ at a rate of 40 sccm (i.e., a HBr:Cl₂ flow ratio ofabout 1:1), N₂ at a rate of 20 sccm, 1100 W of plasma power, 20 W ofbias power, a wafer temperature of 45° C., and a pressure of 4 mTorr.

During step 106, the etched material combines with components of theetchant chemistry, as well as with components of the mask 214 andby-products of the etch process to form a halogen-containing residue218. The halogen-containing residue 218 deposits on the surfaces of thefilm stack 202 and elsewhere on the wafer 200. When exposed toatmospheric gases and water vapor, the halogen-containing residue 218releases (or “outgases”) gaseous reactants, such as bromine, chlorine,hydrogen chloride (HCl), and the like. Such reactants may causecorrosion and particle contamination of the processing equipment andfactory interfaces, as well as metallic layers (e.g., layers of copper(Cu), aluminum (Al), and the like) on the wafer 200. Generally, wafersare transferred between the vacuumed and non-vacuumed regions of theproduction environment using an atmospheric pressure factory interface,such as, e.g., a factory interface of the CENTURA® system (discussed inreference to FIG. 4 below). The halogen-based residue 218 should beoutgassed and/or the residue should be removed from the wafer 200 beforethe wafer is transferred to such factory interface.

In an alternative embodiment (not shown), step 106 further etches andremoves the dielectric layer 204 in the regions 222 to form the gateelectrode 240. Step 106 may use a gas comprising a halogen gas (e.g.,chlorine, hydrogen chloride, and the like) and a reducing gas, such ascarbon monoxide (CO). Such etch process is disclosed in the commonlyassigned U.S. patent application Ser. No. 10/194,566, filed Jul. 12,2002, which is incorporated herein by reference. In this embodiment,step 106 also develops a halogen-containing residue that should beoutgassed and/or removed before the wafer is transferred to thenon-vacuumed factory interface.

At step 108, the wafer 200 is transferred under vacuum using, e.g., arobot of the exemplary CENTURA® system to a remote plasma reactor, suchas the AXIOM® reactor. The AXIOM® reactor is a remote plasma reactor inwhich the radio-frequency plasma is confined such that only reactiveneutrals are allowed to enter a reaction volume of the process chamber.Such confinement scheme precludes plasma-related damage of the substrateor circuits formed on the substrate. In the AXIOM® reactor, a waferbackside may be heated radiantly by quartz halogen lamps or resistivelyheated or cooled using heat transfer (e.g., coolant circulating throughthe wafer support), such that the wafer temperature can be maintained at20 to 450° C. Similar to the referred to above DPS reactor, the AXIOM®reactor may use an endpoint detection system. The AXIOM® reactor isdescribed in detail in U.S. patent application Ser. No. 10/264,664,filed Oct. 4, 2002, which is herein incorporated by reference. Thesalient features of the reactor are briefly described below in referenceto FIG. 3.

At step 110, the halogen-containing residue 218 is outgassed to releasethe halogen-based reactants and, in most applications, removed from thewafer 200 (FIG. 2D). Step 110 comprises sub-step 112 of pre-heating thewafer 200, decision sub-step 114, and decision sub-step 116 of exposingthe wafer to an oxygen-containing gas (e.g., oxygen, water vapor, andthe like) and optionally an additive such as for example nitrogen,argon, helium, and the like. Alternatively, the wafer may be exposed toa hydrogen-containing gas (e.g., hydrogen, forming gas, water vapor,alkanes, alkenes, and the like) and optionally an additive such asoxygen, argon, helium and the like, or sub-step 118 of exposing thewafer to a gas comprising oxygen, nitrogen, and a hydrogen-containinggas, such as at least one of hydrogen (H₂), water vapor (H₂O), and thelike. When the mask 214 is formed from photoresist or APF (both notshown), sub-steps 116 and 118 also simultaneously remove thehalogen-containing residue 218 and the mask.

During step 110, the outgassed halogen-based reactants are converted innon-corrosive volatile compounds that are then pumped out from theprocessing reactor. Upon completion of step 110, the wafer 200 may betransferred for further processing to another processing environmentusing, e.g., the non-vacuumed factory interface that interconnectsvarious vacuumed and non-vacuumed regions of a semiconductor fab.Alternatively, the wafer may be transferred to another processingchamber within the same processing system (e.g., CENTURA® system).

During sub-step 112, the gas is energized to a plasma in the remoteplasma reactor and the wafer 200 is pre-heated to a temperature of atleast 150 degrees to about 400° C. Then, the wafer is maintained at suchtemperature during the remaining portion of step 110. Alternatively, thewafer may be heated and processed simultaneously for improvedthroughput.

In one embodiment, the wafer 200 is pre-heated, to about 250° C. in agas mixture of oxygen and nitrogen. Oxygen and nitrogen are provided fora duration of about 10-20 sec to the chamber at flow rates of about 5000sccm and 500 sccm, respectively (i.e., at O₂:N₂flow ratio of about 10:1)at a pressure greater than 1 Torr.

At sub-step 114, the method 100 queries whether the halogen-containingresidue 218 comprises bromine. Generally, the residue 218 may containbromine when step 106 uses a bromine-containing gas, e.g., hydrogenbromide. In a computerized etch reactor, such as the exemplary DPSreactor, at sub-step 114, the decision making routine may be automatedusing, e.g., a residual gas analyzer (RGA). If the query of step 116 isaffirmatively answered, the method 100 proceeds to sub-step 116 or, whenthe query of sub-step 114 is negatively answered, the method 100proceeds to sub-step 118.

At sub-step 116, the wafer 200 is exposed to reactants that are formedfrom a source gas by the plasma source of a remote plasma reactor, e.g.,source 306 of the AXIOM® reactor. In one illustrative embodiment,sub-step 116 provides the source gas comprising oxygen and nitrogen atflow rates of about 1000 to 9000 sccm and about 100 to 900 sccmrespectively (i.e at O₂:N₂ flow ratio of about 10:1). Further, sub-step116 applies 3000 to 5000 W at about 200 to 600 kHz to form the remoteplasma, maintains a wafer temperature between at least 150 and about400° C. and a gas pressure in the process chamber at about 0.5 to 2Torr. The duration of substep 116 is generally about 15 to 60 sec.

One exemplary process provides 3500 sccm of O₂ and 350 sccm of N₂ (i.e.,a O₂:N₂ flow ratio of about 10:1), 5000 W of plasma power, a wafertemperature of 250° C., a gas pressure of 0.7 Torr, and has a durationof 20 sec. Such process reduces the amount of bromine on the 300 mmwafer from about 250 μg (photoresist mask 214) or about 50-70 μg (hardmask 214) to about or below the detection limit of 3-5 μg. It isbelieved that, during sub-step 116, the remaining portion (i.e., traces)of bromine becomes oxidized and trapped on the sidewalls of thepolysilicon electrode 216.

When the halogen-containing residue 218 comprises a combination ofchlorine and bromine, the process of sub-steps 112 and 116 reduces theamount of chlorine from about 300-350 μg to about 5 μg (photoresist mask214) and to about 10 μg (hard mask 214). However, when thehalogen-containing residue 218 comprises chlorine and does not comprisebromine (e.g., step 106 uses a bromine-free gas), the amount of chlorineon the wafer 200 may be as high as 1000 to 3000 μg. In this application,sub-step 116 can reduce the amount of chlorine on the wafer only by afactor of 5-6 (i.e., to about 200-600 μg).

At sub-step 118, the wafer 200 having the halogen-containing residue 218that does not comprise bromine but comprises chlorine is exposed to thereactants formed by the plasma source of the remote plasma reactor froma source gas comprising oxygen, and a reducing gas to facilitate formingvolatile components. The reducing gas may consist of ahydrogen-containing gas such as hydrogen, forming gas (2-5% hydrogen innitrogen, and in one embodiment, about 4% hydrogen in nitrogen), watervapor, and the like.

In one illustrative embodiment, sub-step 118 provides oxygen at a flowrate of about 1500 to 10,000 sccm and hydrogen-containing gas at a flowrate of about 10 to 2000 sccm (i.e., at O₂:H₂ flow ratio of from about150:1 and 5:1, and H₂:(H₂ or H₂O) flow ratio of from about 2:1 and 1:1).Further, sub-step 118 applies 3000 to 6000 W at about 200 to 600 kHz toform the remote plasma and maintains a wafer temperature between atleast 50 and about 450° C. and a gas pressure in the process chamber atabout 0.5 to 2 Torr. The duration of sub-step 118 is generally about 15to 60 sec.

One exemplary process provides 3500 sccm of O₂ and 800 sccm of forminggas (i.e. O₂:forming gas flow ratio of about 5:1, 5000 W of plasmapower, a wafer temperature of 250° C., a gas pressure of 0.7 Torr, andhas a duration of 20 to 40 sec. Such process reduces the amount ofchlorine on the wafer 200 from about 2000-3000 μg to about 7-10 μg.

One exemplary process provides 1000 to 9000 sccm of O₂ and 100 to 3000sccm of water vapor, (i.e. O₂:water vapor ratio of about 10:1 to 3:1),1000 to 6000 W of plasma power, a wafer temperature of 250° C., a gaspressure of 0.5 to 4 Torr, and has a duration of 20 to 60 sec. Suchprocess reduces the amount of chlorine on the wafer 200 from about2000-3000 μg to about 7-10 μg.

Another exemplary process provides 3500 sccm of O₂ and 500 sccm of watervapor (i.e. O₂:water vapor flow ratio of 7:1), 5000 W of plasma power, awafer temperature of 250° C., a gas pressure of 0.7 Torr, and has aduration of 20 sec. Such process reduces the amount of chlorine on thewafer 200 from about 2000-3000 μg to about 7-10 μg.

Another exemplary process provides 500 to 5000 sccm of forming gas, 5000W of plasma power, a wafer temperature of 250° C., a gas pressure of 0.7Torr, and has a duration of 20 to 40 sec. Such process reduces theamount of chlorine on the wafer 200 from about 2000-3000 μg to about7-10 μg.

In one particular embodiment, an exemplary process provides 1000 sccm offorming gas, 5000 W of plasma power, a wafer temperature of 250° C., agas pressure of 0.7 Torr, and has a duration of 20 to 40 sec. Suchprocess reduces the amount of chlorine on the wafer 200 from about2000-3000 μg to about 7-10 μg.

Another exemplary process provides 100 to 3000 sccm water vapor, 1000 to6000 W of plasma power, a wafer temperature of 250° C., a gas pressureof 0.5 to 4 Torr, and has a duration of 20 to 60 sec. Such processreduces the amount of chlorine on the wafer 200 from about 2000-3000 μgto about 7-10 μg.

In one particular embodiment, an exemplary process provides 500 sccm ofwater vapor, 5000 W of plasma power, a wafer temperature of 250° C., agas pressure of 0.7 Torr, and has a duration of 20 sec. Such processreduces the amount of chlorine on the wafer 200 from about 2000-3000 μgto about 7-10 μg.

Robust rapid bromine removal requires a high temperature (150-400° C.)and plasma. Inert plasma such as argon, nitrogen, helium and the likemay be used. The oxidizing plasma such as O₂ also removes photoresistfor cases where a photoresist mask is present. Other oxidizers such aswater vapor and ozone are also suitable. Oxidizing gases also oxidizeall surfaces of the wafer. Additive gases such as nitrogen, argon,helium and water vapor and the like enhance the lifetime of the oxygenradicals.

Robust rapid chlorine (no bromine in etch process) removal requires ahigh temperature (150-400° C.) and a hydrogen containing plasma. Apurely reducing plasma such as hydrogen, forming gas and water vapor andthe like may be used. The oxidizing plasma such as O₂, water vapor andozone also removes photoresist for cases where a photoresist mask ispresent. The oxidation process creates an oxide barrier between anyresidual chlorine (not removed by the reducing gas) and the atmosphericmoisture when the wafer is removed from the vacuum environment. Oneembodiment uses gas mixture comprising oxygen and forming gas for bothchlorine reduction and oxide barrier formation.

High productivity of step 110 allows, using an integrated semiconductorwafer processing system such as the CENTURA® system, to have one remoteplasma reactor (AXIOM® reactor) for removing the halogen-containingresidue and several plasma etch reactors (e.g., the DPS reactors) foretching the polysilicon and high-K dielectrics (discussed in referenceto FIG. 4 below). Alternatively, this process is suitable for use duringSTI fabrication.

At step 120, the method 100 ends.

FIG. 3 depicts a schematic diagram of the AXIOM® reactor 300 that may beused to practice portions of the method 100. The reactor 300 comprises aprocess chamber 302, a remote plasma source 306, and a controller 308.

The process chamber 302 generally is a vacuum vessel, which comprises afirst portion 310 and a second portion 312. In one embodiment, the firstportion 310 comprises a substrate pedestal 304, a sidewall 316 and avacuum pump 314. The second portion 312 comprises a lid 318 and a gasdistribution plate (showerhead) 320, which defines a gas mixing volume322 and a reaction volume 324. The lid 318 and sidewall 316 aregenerally formed from a metal (e.g., aluminum (Al), stainless steel, andthe like) and electrically coupled to a ground reference 360.

The substrate pedestal 304 supports a substrate (wafer) 326 within thereaction volume 324. In one embodiment, the substrate pedestal 304 maycomprise a source of radiant heat, such as gas-filled lamps 328, as wellas an embedded resistive heater 330 and a conduit 332. The conduit 332provides cooling water from a source 334 to the backside of thesubstrate pedestal 304. The wafer sits on the pedestal surface. Gasconduction transfers heat from the pedestal 304 to the wafer 326. Thetemperature of the wafer 326 may be controlled between about 20 and 400°C.

The vacuum pump 314 is adapted to an exhaust port 336 formed in thesidewall or a bottom wall 316 of the process chamber 302. The vacuumpump 314 is used to maintain a desired gas pressure in the processchamber 302, as well as evacuate the post-processing gases and othervolatile compounds from the chamber. In one embodiment, the vacuum pump314 comprises a throttle valve 338 to control a gas pressure in theprocess chamber 302.

The process chamber 302 also comprises conventional systems forretaining and releasing the wafer 326, detecting an end of a process,internal diagnostics, and the like. Such systems are collectivelydepicted in FIG. 3 as support systems 340.

The remote plasma source 306 comprises a power source 346, a gas panel344, and a remote plasma chamber 342. In one embodiment, the powersource 346 comprises a radio-frequency (RF) generator 348, a tuningassembly 350, and an applicator 352. The RF generator 348 is capable ofproducing of about 200 to 6000 W at a frequency of about 200 to 600 kHz.The applicator 352 is inductively coupled to the remote plasma chamber342 to inductively couple RF power to process gas (or gas mixture) 364to form a plasma 362 in the chamber. In this embodiment, the remoteplasma chamber 342 has a toroidal geometry that confines the plasma andfacilitates efficient generation of radical species, as well as lowersthe electron temperature of the plasma. In other embodiments, the remoteplasma source 306 may be a microwave plasma source, however, thestripping rates are generally higher using the inductively coupledplasma.

The gas panel 344 uses a conduit 366 to deliver the process gas 364 tothe remote plasma chamber 342. The gas panel 344 (or conduit 366)comprises means (not shown), such as mass flow controllers and shut-offvalves, to control gas pressure and flow rate for each individual gassupplied to the chamber 342. In the plasma 362, the process gas 364 isionized and dissociated to form reactive species.

The reactive species are directed into the mixing volume 322 through aninlet port 368 in the lid 318. To minimize charge-up plasma damage todevices on the wafer 326, the ionic species of the process gas 364 aresubstantially neutralized within the mixing volume 322 before the gasreaches the reaction volume 324 through a plurality of openings 370 inthe showerhead 320.

The controller 308 comprises a central processing unit (CPU) 354, amemory 356, and a support circuit 358. The CPU 354 may be of any form ofa general-purpose computer processor used in an industrial setting.Software routines can be stored in the memory 356, such as random accessmemory, read only memory, floppy or hard disk, or other form of digitalstorage. The support circuit 358 is conventionally coupled to the CPU354 and may comprise cache, clock circuits, input/output sub-systems,power supplies, and the like.

The software routines, when executed by the CPU 354, transform the CPUinto a specific purpose computer (controller) 308 that controls thereactor 300 such that the processes are performed in accordance with thepresent invention. The software routines may also be stored and/orexecuted by a second controller (not shown) that is located remotelyfrom the reactor 300.

FIG. 4 is a schematic, top plan view of the exemplary CENTURA®integrated processing system 400. The particular embodiment of thesystem 400 is provided to illustrate the invention and should not beused to limit the scope of the invention.

The system 400 generally includes load-lock chambers 422, processchambers 410, 412, 414, 416, 420, and a robot 430. The load-lockchambers 422 protect vacuumed plenum 428 (or buffer chamber) of thesystem 400 from atmospheric contaminants. The robot 430 uses a blade 434to transfer the substrates between the load lock chambers and processchambers. At least one of the process chambers is a DPS chamberdescribed above in reference to step 106. Further, one or more processchambers may be the AXIOM® chambers described above in reference to step110. Optionally, at least one of the process chambers may be anannealing chamber or other thermal processing chamber, such as theRADIANCE™ chamber available from Applied Materials, Inc (also mentionHART etch chamber from AMHT). The system 400 may also comprise othertypes of process chambers and/or interfaces to processing systems.Further, the system 400 may comprise one or more external metrologychambers 418 connected thereto using, e.g., a terminal 426 of a factoryinterface 424. The factory interface 424 is an atmospheric pressureinterface that is used to transfer cassettes with the pre-processed andpost-processed wafers between various processing systems andmanufacturing regions within a semiconductor fabrication process.

The system controller 436 is coupled to and controls each module of theintegrated processing system 400. Generally the system controller 436controls all aspects of operation of the system 400 using a directcontrol of modules and apparatus of the system 400, or alternatively, bycontrolling the computers associated with these modules and apparatus.In operation, the system controller 436 enables feedback from therespective modules and apparatus to optimize substrate throughput.

The system controller 436 comprises a central processing unit (CPU) 438,a memory 440, and a support circuit 442. The CPU 438 may be one of anyform of a general purpose computer processor that can be used in anindustrial setting. The support circuit 442 is conventionally coupled tothe CPU 438, and may comprise cache, clock circuits, input/outputsubsystems, power supplies, and the like. The software routines, whenexecuted by the CPU 438, transform the CPU into a specific purposecompute (controller) 436. The software routines may also be storedand/or executed by a second controller (not shown) that is locatedremotely from the system 400.

One example of a possible configuration of the system 400 for removinghalogen-containing residue in accordance with the present inventionincludes two load-lock chambers (chambers 422), the PRECLEAN II™ chamber(chamber 410), the AXIOM® chamber (chamber 414), three DPS chambers(chambers 412, 416 and 420), and the metrology chamber (chamber 418).

The invention may be practiced in other semiconductor systems whereinthe processing parameters may be adjusted to achieve acceptablecharacteristics by those skilled in the arts by utilizing the teachingsdisclosed herein without departing from the spirit of the invention.

Although the foregoing discussion refers to the fabrication of the gatestructure of a field effect transistor, fabrication of other devicesused in the integrated circuits can benefit from the invention.

While the foregoing is directed to the illustrative embodiment of thepresent invention, other and further embodiments of the invention may bedevised without departing from the basic scope thereof, and the scopethereof is determined by the claims that follow.

1. An integrated processing system for removing from a substrate ahalogen-containing residue, the residue formed during etching of thesubstrate, the system comprising: a central transfer chamber; at leastone load lock chamber coupled to the central transfer chamber; an etchchamber coupled to the central transfer chamber; a residue removalchamber coupled to the central transfer chamber and adapted to removethe halogen-containing residue, the residue removal chamber having aremote plasma source coupled thereto and a substrate heater configuredto maintain the temperature of a substrate disposed in the residueremoval chamber between 50° C. and 400° C.; a robot disposed in thetransfer chamber and adapted to transfer the substrate between the loadlock chamber, the etch chamber and the residue removal chamber; and acontroller for controlling operation of the system.
 2. The system ofclaim 1, further comprising: at least one of an oxygen-containing or ahydrogen-containing gas source coupled to the residue removal chamberfor providing a gas mixture thereto.
 3. The system of claim 1, furthercomprising: a power source inductively coupled to the remote plasmasource to form a plasma from the gas mixture.
 4. The system of claim 3,wherein the power source is configured to produce an RF signal having afrequency of about 200 to 600 kHz.
 5. The system of claim 3, wherein thepower source is capable of producing an RF signal having a power ofabout 200 to 6000 W.
 6. The system of claim 3, wherein the power sourcefurther comprises a toroidal geometry that confines the plasma.
 7. Thesystem of claim 3, wherein the residue removal chamber furthercomprises: a reaction volume for processing a substrate therein; and amixing volume where ionic species of a process gas are substantiallyneutralized during processing before the process gas reaches thereaction volume.
 8. The system of claim 1, wherein the remote plasmasource further comprises a microwave plasma source.
 9. The system ofclaim 1, further comprising: a pre-clean chamber coupled to the centraltransfer chamber; two additional etch chambers coupled to the centraltransfer chamber; and a metrology chamber coupled to the load lockchamber.
 10. The system of claim 1, wherein the controller furthercomprises a computer readable media having instructions that, whenexecuted, cause the residue removal chamber to: heat the etchedsubstrate disposed in the residue removal chamber to a temperature of atleast 50° C.; and expose the heated substrate to reactants formed by theremote plasma source to remove the halogen-containing residue.
 11. Thesystem of claim 1, wherein the controller further comprises a computerreadable media having instructions that, when executed, cause theresidue removal chamber to: heat the etched substrate disposed in theresidue removal chamber to a temperature of at least 50° C. in anon-plasma gas mixture comprising oxygen and nitrogen; and expose theheated substrate to a plasma that removes the halogen-containingresidue.
 12. The system of claim 1, wherein the controller furthercomprises a computer readable media having instructions that, whenexecuted, cause the residue removal chamber to: heat the etchedsubstrate disposed in the residue removal chamber to a temperature of atleast 50° C.; and expose the heated substrate to a plasma formed fromhydrogen, water vapor, oxygen, and nitrogen that removes thehalogen-containing residue.
 13. An integrated processing system forremoving from a substrate a halogen-containing residue, the residueformed during etching of the substrate, the system comprising: a centraltransfer chamber having a substrate transfer robot disposed therein; atleast one load lock chamber coupled to the central transfer chamber;three etch chambers coupled to the central transfer chamber; a residueremoval chamber coupled to the central transfer chamber and adapted toremove the halogen-containing residue, the residue removal chamberhaving a substrate heater configured to maintain the temperature of asubstrate disposed in the residue removal chamber between 50° C. and400° C. and a remote plasma source coupled to the residue removalchamber and having an inductively coupled power source to form a plasmafrom the gas mixture; at least one of an oxygen-containing or ahydrogen-containing gas source coupled to the residue removal chamberfor providing a gas mixture thereto; and a controller for adjusting theparameters of the system as a function of the measurements performed byan optical metrology tool.
 14. The system of claim 13, furthercomprising: a pre-clean chamber coupled to the central transfer chamber.15. The system of claim 13, wherein the power source is configured toproduce about 200 to 6000 W of RF power having a frequency of about 200to 600 kHz.
 16. The system of claim 13, wherein the controller furthercomprises a computer readable media having instructions that, whenexecuted, cause the residue removal chamber to: heat the etchedsubstrate disposed in the residue removal chamber to a temperature of atleast 50° C.; and expose the heated substrate to reactants formed by theremote plasma source to remove the halogen-containing residue.
 17. Thesystem of claim 13, wherein the controller further comprises a computerreadable media having instructions that, when executed, cause theresidue removal chamber to: heat the etched substrate disposed in theresidue removal chamber to a temperature of at least 50° C. in anon-plasma gas mixture comprising oxygen and nitrogen; and expose theheated substrate to a plasma that removes the halogen-containingresidue.
 18. The system of claim 13, wherein the controller furthercomprises a computer readable media having instructions that, whenexecuted, cause the residue removal chamber to: heat the etchedsubstrate disposed in the residue removal chamber to a temperature of atleast 50° C.; and expose the heated substrate to a plasma formed fromhydrogen, water vapor, oxygen, and nitrogen that removes thehalogen-containing residue.